Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor memory device and a method for manufacturing the same.
Portable mobile devices small in size and miniaturized digital home appliances are widely in use. In coping with such trends, the semiconductor memory devices for use in mobile devices or digital home appliances are highly integrated. Particularly for DRAM or flash memory devices, it is an on-going effort to find ways to store a larger quantity of information in a limited space. The basic components of a DRAM device are transistors and capacitors. The transistor and capacitor are made in a stack structure, in which the transistor is formed on a silicon semiconductor substrate and the capacitor is formed on the transistor.
For electrical connection between the transistor and the capacitor, a storage node contact is disposed between a source region of the transistor and a lower electrode of the capacitor. In addition, a drain region of the transistor is electrically connected to a bit line through a bit line contact. In the structure in which the capacitor is disposed on the planar type transistor, films for signal transmission (for example, a word line and a bit line) are disposed between the transistor and the capacitor. Hence, there is a limit to increasing the capacity of the capacitor due to the space occupied by the films. Moreover, as a gate width of the planar type transistor is narrowed to less than 40 nm, a larger amount of power is consumed and an amount of a body current, which is a leakage current between the source region and the drain region of the transistor, is abruptly increased. To overcome these limitations associated with planar type transistors, the concept of vertical transistors has been studied.
FIG. 1 is drawn to show the basic vertical transistor concept. Referring to FIG. 1, the vertical transistor 100 has a drain region 112 formed at the lower portion of the semiconductor substrate 110 with respect to the gate electrode 120 and a source region 114 formed at the upper portion of the semiconductor substrate 110 with respect to the gate electrode 120. A channel region 116 is formed in the semiconductor substrate 110 in a vertical direction between the drain region 112 and the source region 114. A gate dielectric film 118 and the gate electrode 120 are sequentially disposed over the channel region 116 on the lateral side of the semiconductor substrate 110. When the vertical transistor 100 is applied to a DRAM device, a bit line is coupled to the drain region 112 and a storage node is coupled to the source region 114. The bit line is disposed so as to be buried in the lower side portion of the semiconductor substrate 110, and, unlike the planar type transistor, the space for forming the storage node is not reduced. Thus, the data storage capacity may not be suppressed in spite of the high degree of integration.
However, in order to form a vertical transistor as described above, it is necessary to form the drain region 112 at one side of the semiconductor substrate 110 on the lower portion with respect to the gate electrode 120. This process is not easy. For example, before forming the drain region 112, a conductive film doped at a high concentration is formed on the portion of the silicon substrate 110 where the drain region 112 is to be formed (that is, on the side of the lower portion of the silicon substrate 110 with respect to the gate electrode 120). Then, the dopants doped in the conductive film are diffused into the lower portion of the semiconductor substrate 110 to thereby form the drain region 112. However, with high integration of semiconductor devices resulting in overall size reduction of the semiconductor devices, it is difficult to form the drain region 112 of the vertical transistor 110 for accurate size and positioning in the semiconductor substrate 110.